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k4s561633c-rl(n) rev. 0.7 dec. 2001 cmos sdram 16mx16 revision 0.7 december 2001 sdram 54csp (v dd /v ddq 3.0v/3.0v & 3.3v/3.3v)
k4s561633c-rl(n) rev. 0.7 dec. 2001 cmos sdram revision history revision 0.0 (april 4. 2001, target) ? first generation of 256mb low power sdram without special function(v dd 3.0v, v ddq 3.0v). revision 0.1 (june 4. 2001, target) ? addition of dc current value. revision 0.2 (june 20. 2001, target) ? changed device name from low power sdram to mobile dram. revision 0.3 (august 10. 2001, preliminary) ? change of tsac from 6ns to 6.5ns in case of -1l part, from 7ns to 7.5ns in case of -15 part. ? change of toh from 3ns to 3.5ns. ? change v ih min. from 2.0v to 0.8xv ddq and v oh min. from 2.4v to 0.9xv ddq revision 0.4 (october 6. 2001, preliminary) ? changed dc current. ? changed of cl2 tsac from 6ns to 7ns for -75 part. ? changed of cl3 tsac from 6ns to 7ns and cl2 tsac from 6ns to 8ns, cl1 tsac from 18ns to 20ns for -1l part. ? changed of toh from 3ns to 2.5ns. ? changed of tss from 2.5ns to 2.0ns for -75 part and from 3.0ns to 2.5ns for -1l part. ? integration of vddq 1.8v device and 2.5v device. ? change vih min. from 0.8xvddq to 0.9xvddq and voh min. from 0.9xvddq to 0.95xvddq. ? change vil max. from 0.8v to 0.3v and vol min. from 0.4v to 0.2v. ? change ioh from -0.1ma to -2ma and iol from 0.1ma to 2ma. ? erase -15 bin and add -1h bin. revision 0.5 (october 12. 2001, preliminary) ? changed vih min. from 0.9xvddq to 2.0v and voh min. from 0.95xvddq to 2.4v. ? changed vil max. from 0.3v to 0.8v and vol min. from 0.2v to 0.4v. revision 0.6 (november 7. 2001, preliminary) ? changed vih min. from 2.0v to 2.2v and vil max. from 0.8v to 0.5v. revision 0.7 (december 3. 2001, final) ? final specification.
k4s561633c-rl(n) rev. 0.7 dec. 2001 cmos sdram ? 3.0v power supply. ? lvttl compatible with multiplexed address. ? four banks operation. ? mrs cycle with address key programs. -. cas latency (1 & 2 & 3). -. burst length (1, 2, 4, 8 & full page). -. burst type (sequential & interleave). ? emrs cycle with address key programs. ? all inputs are sampled at the positive going edge of the system clock. ? dqm for masking. ? auto refresh. ? 64ms refresh period (8k cycle). ? commercial temperature operation (-25?c ~ 70?c). extended temperature operation ( -25?c ~ 85?c). features general description 4m x 16bit x 4 banks synchronous dram in 54csp functional block diagram the k4s561633c is 268,435,456 bits synchronous high data rate dynamic ram organized as 4 x 4,196,304 words by 16 bits, fabri- cated with samsung ' s high performance cmos technology. syn- chronous design allows precise cycle control with the use of system clock and i/o transactions are possible on every clock cycle. range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. bank select data input register 4m x 16 4m x 16 s e n s e a m p o u t p u t b u f f e r i / o c o n t r o l column decoder latency & burst length programming register a d d r e s s r e g i s t e r r o w b u f f e r r e f r e s h c o u n t e r r o w d e c o d e r c o l . b u f f e r l r a s l c b r lcke lras lcbr lwe ldqm clk cke cs ras cas we l(u)dqm lwe ldqm dqi clk add lcas lwcbr 4m x 16 4m x 16 timing register * samsung electronics reserves the right to change products or specification without notice. ordering information part no. max freq. interface package k4s561633c-rl/n75 133mhz(cl=3) lvttl 54 csp k4s561633c-rl/n1h 100mhz(cl=2) k4s561633c-rl/n1l 100mhz(cl=3) *1 -rn ;low power, operating temperature : -25?c ~ 85?c. -rl ; low power, operating temperature : -25?c ~ 70?c. 1. in case of 33mhz frequency, cl1 can be supported. note :
k4s561633c-rl(n) rev. 0.7 dec. 2001 cmos sdram 54ball(6x9) csp 1 2 3 7 8 9 a v ss dq15 v ssq v ddq dq0 v dd b dq14 dq13 v ddq v ssq dq2 dq1 c dq12 dq11 v ssq v ddq dq4 dq3 d dq10 dq9 v ddq v ssq dq6 dq5 e dq8 nc v ss v dd ldqm dq7 f udqm clk cke cas ras we g a12 a11 a9 ba0 ba1 cs h a8 a7 a6 a0 a1 a10 j v ss a5 a4 a3 a2 v dd pin name pin function clk system clock cs chip select cke clock enable a 0 ~ a 12 address ba 0 ~ ba 1 bank select address ras row address strobe cas column address strobe we write enable l(u)dqm data input/output mask dq 0 ~ 15 data input/output v dd /v ss power supply/ground v ddq /v ssq data output power/ground package dimension and pin configuration symbol min typ max a 0.90 0.95 1.00 a 1 0.30 0.35 0.40 e - 8.10 - e 1 - 6.40 - d - 15.10 - d 1 - 6.40 - e - 0.80 - j b 0.40 0.45 0.50 z - - 0.08 [unit:mm] 5 2 1 6 3 4 8 9 7 f e d c b j h g a e d d / 2 d 1 e 1 e e/2 a a1 z j b encapsulant max. 0.20 k 4 s 5 6 1 6 3 3 c s a m s u n g w e e k #a1 ball origin indicator < bottom view *1 > < top view *2 > < top view *2 > *1: bottom view *2: top view
k4s561633c-rl(n) rev. 0.7 dec. 2001 cmos sdram dc operating conditions recommended operating conditions (voltage referenced to v ss = 0v, t a =0 c ~ 70 c (commercial), -25 c ~ 85 c (extended)) parameter symbol min typ max unit note supply voltage v dd 2.7 3.0 3.6 v v ddq 2.7 3.0 3.6 v input logic high voltage v ih 2.2 3.0 v ddq +0.3 v 1 input logic low voltage v il -0.3 0 0.5 v 2 output logic high voltage v oh 2.4 - - v i oh = -2ma output logic low voltage v ol - - 0.4 v i ol = 2ma input leakage current i li -10 - 10 ua 3 capacitance (v dd = 3.0v & 3.3v, t a = 23 c, f = 1mhz, v ref =0.9v 50 mv) pin symbol min max unit note clock c clk 2.0 4.0 pf ras , cas , we , cs , cke, dqm c in 2.0 4.0 pf address c add 2.0 4.0 pf dq 0 ~ dq 15 c out 3.5 6.0 pf 1. v ih (max) = 5.3v ac. the overshoot voltage duration is 3ns. 2. v il (min) = -2.0v ac. the undershoot voltage duration is 3ns. 3. any input 0v v in v ddq . input leakage currents include hi-z output leakage for all bi-directional buffers with tri-state outputs. 4. dout is disabled, 0v v out v ddq. note : absolute maximum ratings parameter symbol value unit voltage on any pin relative to vss v in , v out -1.0 ~ 4.6 v voltage on v dd supply relative to vss v dd , v ddq -1.0 ~ 4.6 v storage temperature t stg -55 ~ +150 c power dissipation p d 1 w short circuit current i os 50 ma permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restricted to recommended operating condition. exposure to higher than recommended voltage for extended periods of time could affect device reliability. note :
k4s561633c-rl(n) rev. 0.7 dec. 2001 cmos sdram dc characteristics recommended operating conditions (voltage referenced to v ss = 0v, t a =-25 c ~ 70 c (commercial), -25 c ~ 85 c (extended)) parameter symbol test condition version unit note -75 -1h -1l operating current (one bank active) i cc1 burst length = 1 t rc 3 t rc (min) i o = 0 ma 90 85 85 ma 1 precharge standby current in power-down mode i cc2 p cke v il (max), t cc = 10ns 0.5 ma i cc2 ps cke & clk v il (max), t cc = 0.5 precharge standby current in non power-down mode i cc2 n cke 3 v ih (min), cs 3 v ih (min), t cc = 10ns input signals are changed one time during 20ns 15 ma i cc2 ns cke 3 v ih (min), clk v il (max), t cc = input signals are stable 10 active standby current in power-down mode i cc3 p cke v il (max), t cc = 10ns 6 ma i cc3 ps cke & clk v il (max), t cc = 6 active standby current in non power-down mode (one bank active) i cc3 n cke 3 v ih (min), cs 3 v ih (min), t cc = 10ns input signals are changed one time during 20ns 25 ma i cc3 ns cke 3 v ih (min), clk v il (max), t cc = input signals are stable 25 ma operating current (burst mode) i cc4 i o = 0 ma page burst 4banks activated t ccd = 2clks 130 130 105 ma 1 refresh current i cc5 t rc 3 t rc (min) 185 185 165 ma 2 self refresh current i cc6 cke 0.2v -rl 800 ua 3 -rn ua 4 1. measured with outputs open. 2. refresh period is 64ms. 3. k4s561633c-rl** 4. k4s561633c-rn** 5. unless otherwise noted, input swing ievei is cmos(v ih /v il =v ddq /v ssq) notes :
k4s561633c-rl(n) rev. 0.7 dec. 2001 cmos sdram operating ac parameter (ac operating conditions unless otherwise noted) parameter symbol version unit note - 75 -1h -1l row active to row active delay t rrd (min) 15 20 20 ns 1 ras to cas delay t rcd (min) 20 20 24 ns 1 row precharge time t rp (min) 20 20 24 ns 1 row active time t ras (min) 45 50 60 ns 1 t ras (max) 100 us row cycle time t rc (min) 65 70 84 ns 1 last data in to row precharge t rdl (min) 2 clk 2 last data in to active delay t dal (min) 2 clk + trp - last data in to new col. address delay t cdl (min) 1 clk 2 last data in to burst stop t bdl (min) 1 clk 2 col. address to col. address delay t ccd (min) 1 clk 3 number of valid output data cas latency=3 2 ea 4 cas latency=2 1 cas latency=1 - 0 ac operating test conditions (v dd = 2.7v ~ 3.6v, t a =-25 c ~ 70 c (commercial), -25 c ~ 85 c (extended)) parameter value unit ac input levels (vih/vil) 2.4 / 0.4 v input timing measurement reference level 0.5 x v ddq v input rise and fall time tr/tf = 1/1 ns output timing measurement reference level 0.5 x v ddq v output load condition see fig. 2 1. the minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. minimum delay is required to complete write. 3. all parts allow every cycle column address change. 4. in case of row precharge interrupt, auto precharge and read burst stop. notes : vddq 1200 w 870 w output 30pf v oh (dc) = 2.4v , i oh = -2ma v ol (dc) = 0.4v, i ol = 2ma vtt = 0.5 x vddq 50 w output 30pf z0 = 50 w (fig. 2) ac output load circuit (fig. 1) dc output load circuit
k4s561633c-rl(n) rev. 0.7 dec. 2001 cmos sdram 1. parameters depend on programmed cas latency. 2. if clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. assumed input rise and fall time (tr & tf) = 1ns. if tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter. notes : ac characteristics (ac operating conditions unless otherwise noted) parameter symbol - 75 -1h -1l unit note min max min max min max clk cycle time cas latency=3 t cc 7.5 1000 10 1000 10 1000 ns 1 cas latency=2 10 10 12 cas latency=1 - - 25 clk to valid output delay cas latency=3 t sac 5.4 7 7 ns 1,2 cas latency=2 7 7 8 cas latency=1 - - 20 output data hold time cas latency=3 t oh 2.5 2.5 2.5 ns 2 cas latency=2 2.5 2.5 2.5 cas latency=1 - - 2.5 clk high pulse width t ch 2.5 3 3 ns 3 clk low pulse width t cl 2.5 3 3 ns 3 input setup time t ss 2.0 2.5 2.5 ns 3 input hold time t sh 1.0 1.5 1.5 ns 3 clk to output in low-z t slz 1 1 1 ns 2 clk to output in hi-z cas latency=3 t shz 5.4 7 7 ns cas latency=2 7 7 8 cas latency=1 - - 20
k4s561633c-rl(n) rev. 0.7 dec. 2001 cmos sdram simplified truth table (v=valid, x=don t care, h=logic high, l=logic low) command cken-1 cken cs ras cas we dqm ba 0,1 a 10 /ap a 11, a 12, a 9 ~ a 0 note register mode register set h x l l l l x op code 1, 2 refresh auto refresh h h l l l h x x 3 self refresh entry l 3 exit l h l h h h x x 3 h x x x 3 bank active & row addr. h x l l h h x v row address read & column address auto precharge disable h x l h l h x v l column address (a 0 ~a 8 ) 4 auto precharge enable h 4, 5 write & column address auto precharge disable h x l h l l x v l column address (a 0 ~a 8 ) 4 auto precharge enable h 4, 5 burst stop h x l h h l x x 6 precharge bank selection h x l l h l x v l x all banks x h clock suspend or active power down entry h l h x x x x x l v v v exit l h x x x x x precharge power down mode entry h l h x x x x x l h h h exit l h h x x x x l v v v dqm h x v x 7 no operation command h x h x x x x x l h h h 1. op code : operand code a 0 ~ a 12 & ba 0 ~ ba 1 : program keys. (@mrs) 2. mrs can be issued only at all banks precharge state. a new command can be issued after 2 clk cycles of mrs. 3. auto refresh functions are the same as cbr refresh of dram. the automatical precharge without row precharge command is meant by "auto". auto/self refresh can be issued only at all banks precharge state. 4. ba 0 ~ ba 1 : bank select addresses. if both ba 0 and ba 1 are "low" at read, write, row active and precharge, bank a is selected. if ba 0 is "low" and ba 1 is "high" at read, write, row active and precharge, bank b is selected. if ba 0 is "high" and ba 1 is "low" at read, write, row active and precharge, bank c is selected. if both ba 0 and ba 1 are "high" at read, write, row active and precharge, bank d is selected. if a 10 /ap is "high" at row precharge, ba 0 and ba 1 is ignored and all banks are selected. 5. during burst read or write with auto precharge, new read/write command can not be issued. another bank read/write command can be issued after the end of burst. new row active of the associated bank can be issued at t rp after the end of burst. 6. burst stop command is valid at every burst length. 7. dqm sampled at the positive going edge of clk masks the data-in at that same clk in write operation (write dqm latency is 0), but in read operation makes the data-out hi-z state after 2 clk cycles. (read dqm latency is 2). note :
cmos sdram device operations electronics mobile dram (v dd 2.5v, v ddq 1.8v & 2.5v) normal mrs mode test mode cas latency burst type burst length a8 a7 type a6 a5 a4 latency a3 type a2 a1 a0 bt=0 bt=1 0 0 mode register set 0 0 0 reserved 0 sequential 0 0 0 1 1 0 1 reserved 0 0 1 1 1 interleave 0 0 1 2 2 1 0 reserved 0 1 0 2 mode select 0 1 0 4 4 1 1 reserved 0 1 1 3 ba1 ba0 mode 0 1 1 8 8 write burst length 1 0 0 reserved 0 0 setting for nor- mal mrs 1 0 0 reserved reserved a9 length 1 0 1 reserved 1 0 1 reserved reserved 0 burst 1 1 0 reserved 1 1 0 reserved reserved 1 single bit 1 1 1 reserved 1 1 1 full page reserved full page length : 256(x16) a. mode register field table to program modes register programmed with normal mrs address ba0 ~ ba1 *1 a12 ~ a10/ap a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 function "0" setting for normal mrs rfu w.b.l test mode cas latency bt burst length 1. apply power and start clock, attempt to maintain cke= "h", dqm= "h" and the other pins are nop condition at the inputs. 2. power is applied to vdd and vddq (simultaneously). 3. maintain stable power, stable clock and nop input condition for a minimum of 200us. 4. issue precharge commands for all banks of the devices. 5. issue 2 or more auto-refresh commands. 6. issue a mode register set command to initialize the mode register. note : 1. in order to assert normal mrs, ba0 and ba1 should set "0" absolutely. b. power up sequence
cmos sdram device operations electronics mobile dram (v dd 2.5v, v ddq 1.8v & 2.5v) c. burst sequence initial address sequential interleave a 1 a 0 0 0 1 1 0 1 0 1 0 1 2 3 1 2 3 0 2 3 0 1 3 0 1 2 0 1 2 3 1 0 3 2 2 3 0 1 3 2 1 0 2. burst length = 8 initial address sequential interleave 0 0 0 0 1 1 1 1 0 1 0 1 0 1 0 1 0 1 2 3 4 5 6 7 2 3 4 5 6 7 0 1 4 5 6 7 0 1 2 3 6 7 0 1 2 3 4 5 a 1 a 0 a 2 0 0 1 1 0 0 1 1 1 2 3 4 5 6 7 0 3 4 5 6 7 0 1 2 5 6 7 0 1 2 3 4 7 0 1 2 3 4 5 6 0 1 2 3 4 5 6 7 2 3 0 1 6 7 4 5 4 5 6 7 0 1 2 3 6 7 4 5 2 3 0 1 1 0 3 2 5 4 7 6 3 2 1 0 7 6 5 4 5 4 7 6 1 0 3 2 7 6 5 4 3 2 1 0 1. burst length = 4
cmos sdram device operations electronics mobile dram (v dd 2.5v, v ddq 1.8v & 2.5v) bank addresses (ba0 ~ ba1) : in case x 4 this sdram is organized as four independent banks of 4,194,304 words x 4 bits memory arrays. the ba 0 ~ ba 1 inputs are latched at the time of assertion of ras and cas to select the bank to be used for the operation. the bank addresses ba 0 ~ ba 1 are latched at bank active, read, write, mode register set and pre- charge operations. : in case x 8 this sdram is organized as four independent banks of 2,097,152 words x 8 bits memory arrays. the ba 0 ~ ba 1 inputs are latched at the time of assertion of ras and cas to select the bank to be used for the operation. the bank addresses ba 0 ~ ba 1 are latched at bank active, read, write, mode register set and pre- charge operations. : in case x 16 this sdram is organized as four independent banks of 1,048,576 words x 16 bits memory arrays. the ba 0 ~ ba 1 inputs are latched at the time of assertion of ras and cas to select the bank to be used for the operation. the bank addresses ba 0 ~ ba 1 are latched at bank active, read, write, mode register set and pre- charge operations. address inputs (a0 ~ a11) : in case x 4 the 22 address bits are required to decode the 4,194,304 word locations are multiplexed into 12 address input pins (a 0 ~ a 11 ). the 12 bit row addresses are latched along with ras and ba 0 ~ ba 1 during bank activate command. the 10 bit column addresses are latched along with cas , we and ba 0 ~ ba 1 during read or write command. : in case x 8 the 21 address bits are required to decode the 2,097,152 word locations are multiplexed into 12 address input pins (a 0 ~ a 11 ). the 12 bit row addresses are latched along with ras and ba 0 ~ ba 1 during bank activate command. the 9 bit column addresses are latched along with cas , we and ba 0 ~ ba 1 during read or write command. : in case x 16 the 20 address bits are required to decode the 1,048,576 word locations are multiplexed into 12 address input pins (a 0 ~ a 11 ). the 12 bit row addresses are latched along with ras and ba 0 ~ ba 1 during bank activate command. the 8 bit column addresses are latched along with cas , we and ba 0 ~ ba 1 during read or write command. addresses of 64mb d. device operations bank addresses (ba0 ~ ba1) : in case x 4 this sdram is organized as four independent banks of 8,388,608 words x 4 bits memory arrays. the ba 0 ~ ba 1 inputs are latched at the time of assertion of ras and cas to select the bank to be used for the operation. the bank addresses ba 0 ~ ba 1 are latched at bank active, read, write, mode register set and pre- charge operations. : in case x 8 this sdram is organized as four independent banks of 4,194,304 words x 8 bits memory arrays. the ba 0 ~ ba 1 inputs are latched at the time of assertion of ras and cas to select the bank to be used for the operation. the bank addresses ba 0 ~ ba 1 are latched at bank active, read, write, mode register set and pre- charge operations. : in case x 16 this sdram is organized as four independent banks of 2,097,152 words x 16 bits memory arrays. the ba 0 ~ ba 1 inputs are latched at the time of assertion of ras and cas to select the bank to be used for the operation. the bank addresses ba 0 ~ ba 1 are latched at bank active, read, write, mode register set and pre- charge operations. address inputs (a0 ~ a11) : in case x 4 the 23 address bits are required to decode the 8,388,608 word locations are multiplexed into 12 address input pins (a 0 ~ a 11 ). the 12 bit row addresses are latched along with ras and ba 0 ~ ba 1 during bank activate command. the 11 bit column addresses are latched along with cas , we and ba 0 ~ ba 1 during read or write command. : in case x 8 the 22 address bits are required to decode the 4,194,304 word locations are multiplexed into 12 address input pins (a 0 ~ a 11 ). the 12 bit row addresses are latched along with ras and ba 0 ~ ba 1 during bank activate command. the 10 bit column addresses are latched along with cas , we and ba 0 ~ ba 1 during read or write command. : in case x 16 the 21 address bits are required to decode the 2,097,152 word locations are multiplexed into 12 address input pins (a 0 ~ a 11 ). the 12 bit row addresses are latched along with ras and ba 0 ~ ba 1 during bank activate command. the 9 bit column addresses are latched along with cas , we and ba 0 ~ ba 1 during read or write command. addresses of 128mb
cmos sdram device operations electronics mobile dram (v dd 2.5v, v ddq 1.8v & 2.5v) bank addresses (ba0 ~ ba1) : in case x 4 this sdram is organized as four independent banks of 16,777,216 words x 4 bits memory arrays. the ba 0 ~ ba 1 inputs are latched at the time of assertion of ras and cas to select the bank to be used for the operation. the bank addresses ba 0 ~ ba 1 are latched at bank active, read, write, mode register set and pre- charge operations. : in case x 8 this sdram is organized as four independent banks of 8,388,608 words x 8 bits memory arrays. the ba 0 ~ ba 1 inputs are latched at the time of assertion of ras and cas to select the bank to be used for the operation. the bank addresses ba 0 ~ ba 1 are latched at bank active, read, write, mode register set and pre- charge operations. : in case x 16 this sdram is organized as four independent banks of 4,194,304 words x 16 bits memory arrays. the ba 0 ~ ba 1 inputs are latched at the time of assertion of ras and cas to select the bank to be used for the operation. the bank addresses ba 0 ~ ba 1 are latched at bank active, read, write, mode register set and pre- charge operations. address inputs (a0 ~ a12) : in case x 4 the 24 address bits are required to decode the 16,777,216 word locations are multiplexed into 13 address input pins (a 0 ~ a 12 ). the 13 bit row addresses are latched along with ras and ba 0 ~ ba 1 during bank activate command. the 11 bit column addresses are latched along with cas , we and ba 0 ~ ba 1 during read or write command. : in case x 8 the 23 address bits are required to decode the 8,388,608 word locations are multiplexed into 13 address input pins (a 0 ~ a 12 ). the 13 bit row addresses are latched along with ras and ba 0 ~ ba 1 during bank activate command. the 10 bit column addresses are latched along with cas , we and ba 0 ~ ba 1 during read or write command. : in case x 16 the 22 address bits are required to decode the 4,194,304 word locations are multiplexed into 13 address input pins (a 0 ~ a 12 ). the 13 bit row addresses are latched along with ras and ba 0 ~ ba 1 during bank activate command. the 9 bit column addresses are latched along with cas , we and ba 0 ~ ba 1 during read or write command. addresses of 256mb d. device operations (continued) clock (clk) the clock input is used as the reference for all sdram opera- tions. all operations are synchronized to the positive going edge of the clock. the clock transitions must be monotonic between v il and v ih . during operation with cke high all inputs are assumed to be in a valid state (low or high) for the duration of set-up and hold time around positive edge of the clock in order to function well q perform and i cc specifications. clock enable (cke) the clock enable(cke) gates the clock onto sdram. if cke goes low synchronously with clock (set-up and hold time are the same as other inputs), the internal clock is suspended from the next clock cycle and the state of output and burst address is frozen as long as the cke remains low. all other inputs are ignored from the next clock cycle after cke goes low. when all banks are in the idle state and cke goes low synchronously with clock, the sdram enters the power down mode from the next clock cycle. the sdram remains in the power down mode ignoring the other inputs as long as cke remains low. the power down exit is syn- chronous as the internal clock is suspended. when cke goes high at least "1clk + t ss " before the high going edge of the clock, then the sdram becomes active from the same clock edge accepting all the input commands. nop and device deselect when ras , cas and we are high, the sdram performs no operation (nop). nop does not initiate any new operation, but is needed to complete operations which require more than single clock cycle like bank activate, burst read, auto refresh, etc. the device deselect is also a nop and is entered by asserting cs high. cs high disables the command decoder so that ras , cas , we and all the address inputs are ignored.
cmos sdram device operations electronics mobile dram (v dd 2.5v, v ddq 1.8v & 2.5v) dqm operation the dqm is used to mask input and output operations. it works similar to oe during read operation and inhibits writing during write operation. the read latency is two cycles from dqm and zero cycle for write, which means dqm masking occurs two cycles later in read cycle and occurs in the same cycle during write cycle. dqm operation is synchronous with the clock. the dqm signal is important during burst interruptions of write with read or precharge in the sdram. due to asynchronous nature of the internal write, the dqm operation is critical to avoid unwanted or incomplete writes when the complete burst write is not required. please refer to dqm timing diagram also. mode register set (mrs) the mode register stores the data for controlling the various oper- ating modes of sdram. it programs the cas latency, burst type, burst length, test mode and various vendor specific options to make sdram useful for variety of different applications. the default value of the mode register is not defined, therefore the mode register must be written after power up to operate the sdram. the mode register is written by asserting low on cs , ras , cas and we (the sdram should be in active mode with cke already high prior to writing the mode register). the state of address pins a 0 ~ a n and ba 0 ~ ba 1 in the same cycle as cs , ras , cas and we going low is the data written in the mode reg- ister. two clock cycles is required to complete the write in the mode register. the mode register contents can be changed using the same command and clock cycle requirements during opera- tion as long as all banks are in the idle state. the mode register is divided into various fields depending on the fields of functions. the burst length field uses a 0 ~ a 2 , burst type uses a 3 , cas latency (read latency from column address) use a 4 ~ a 6 , vendor specific options or test mode use a 7 ~ a 8 , a 10 /ap ~ a n and ba 0 ~ ba 1 . the write burst length is programmed using a 9 . a 7 ~ a 8 , a 10 / ap ~ a n and ba 0 ~ ba 1 must be set to low for normal sdram operation. refer to the table for specific codes for various burst length, burst type and cas latencies. d. device operations (continued) bank activate the bank activate command is used to select a random row in an idle bank. by asserting low on ras and cs with desired row and bank address, a row access is initiated. the read or write opera- tion can occur after a time delay of t rcd (min) from the time of bank activation. t rcd is an internal timing parameter of sdram, therefore it is dependent on operating clock frequency. the mini- mum number of clock cycles required between bank activate and read or write command should be calculated by dividing t rcd (min) with cycle time of the clock and then rounding off the result to the next higher integer. the sdram has four internal banks in the same chip and shares part of the internal circuitry to reduce chip area, therefore it restricts the activation of four banks simulta- neously. also the noise generated during sensing of each bank of sdram is high, requiring some time for power supplies to recover before another bank can be sensed reliably. t rrd (min) specifies the minimum time required between activating different bank. the number of clock cycles required between different bank activation must be calculated similar to t rcd specification. the minimum time required for the bank to be active to initiate sensing and restoring the complete row of dynamic cells is determined by t ras (min). every sdram bank activate command must satisfy t ras (min) specification before a precharge command to that active bank can be asserted. the maximum time any bank can be in the active state is determined by t ras (max). the number of cycles for both t ras (min) and t ras (max) can be calculated similar to t rcd specification. burst read the burst read command is used to access burst of data on con- secutive clock cycles from an active row in an active bank. the burst read command is issued by asserting low on cs and cas with we being high on the positive edge of the clock. the bank must be active for at least t rcd (min) before the burst read com- mand is issued. the first output appears in cas latency number of clock cycles after the issue of burst read command. the burst length, burst sequence and latency from the burst read command is determined by the mode register which is already programmed.
cmos sdram device operations electronics mobile dram (v dd 2.5v, v ddq 1.8v & 2.5v) the burst read can be initiated on any column address of the active row. the address wraps around if the initial address does not start from a boundary such that number of outputs from each i/o are equal to the burst length programmed in the mode regis- ter. the output goes into high-impedance at the end of the burst, unless a new burst read was initiated to keep the data output gap- less. the burst read can be terminated by issuing another burst read or burst write in the same bank or the other active bank or a precharge command to the same bank. the burst stop command is valid at every page burst length. burst write the burst write command is similar to burst read command and is used to write data into the sdram on consecutive clock cycles in adjacent addresses depending on burst length and burst sequence. by asserting low on cs , cas and we with valid col- umn address, a write burst is initiated. the data inputs are pro- vided for the initial address in the same clock cycle as the burst write command. the input buffer is deselected at the end of the burst length, even though the internal writing can be completed yet. the writing can be completed by issuing a burst read and dqm for blocking data inputs or burst write in the same or another active bank. the burst stop command is valid at every burst length. the write burst can also be terminated by using dqm for blocking data and procreating the bank t rdl after the last data input to be written into the active row. see dqm operation also. all banks precharge all banks can be precharged at the same time by using precharge all command. asserting low on cs , ras , and we with high on a 10 /ap after all banks have satisfied t ras (min) requirement, per- forms precharge on all banks. at the end of t rp after performing precharge to all the banks, all banks are in idle state. d. device operations (continued) precharge the precharge operation is performed on an active bank by asserting low on cs , ras , we and a 10 /ap with valid ba 0 ~ ba 1 of the bank to be precharged. the precharge command can be asserted anytime after t ras (min) is satisfied from the bank active command in the desired bank. t rp is defined as the minimum number of clock cycles required to complete row precharge is cal- culated by dividing t rp with clock cycle time and rounding up to the next higher integer. care should be taken to make sure that burst write is completed or dqm is used to inhibit writing before precharge command is asserted. the maximum time any bank can be active is specified by t ras (max). therefore, each bank activate command. at the end of precharge, the bank enters the idle state and is ready to be activated again. entry to power down, auto refresh, self refresh and mode register set etc. is possible only when all banks are in idle state. auto precharge the precharge operation can also be performed by using auto precharge. the sdram internally generates the timing to satisfy t ras (min) and "t rp " for the programmed burst length and cas latency. the auto precharge command is issued at the same time as burst read or burst write by asserting high on a 10 /ap. if burst read or burst write by asserting high on a 10 /ap, the bank is left active until a new command is asserted. once auto precharge command is given, no new commands are possible to that partic- ular bank until the bank achieves idle state. auto refresh the storage cells of 64mb, 128mb and 256mb sdram need to be refreshed every 64ms to maintain data. an auto refresh cycle accomplishes refresh of a single row of storage cells. the internal counter increments automatically on every auto refresh cycle to refresh all the rows. an auto refresh command is issued by asserting low on cs , ras and cas with high on cke and we . the auto refresh command can only be asserted with both banks being in idle state and the device is not in power down mode (cke is high in the previous cycle).
cmos sdram device operations electronics mobile dram (v dd 2.5v, v ddq 1.8v & 2.5v) self refresh the self refresh is another refresh mode available in the sdram. the self refresh is the preferred refresh mode for data retention and low power operation of sdram. in self refresh mode, the sdram disables the internal clock and all the input buffers except cke. the refresh addressing and timing are internally generated to reduce power consumption. the self refresh mode is entered from all banks idle state by asserting low on cs , ras , cas and cke with high on we . once the self refresh mode is entered, only cke state being low mat- ters, all the other inputs including the clock are ignored in order to remain in the self refresh mode. the self refresh is exited by restarting the external clock and then asserting high on cke. this must be followed by nop's for a mini- mum time of t rc before the sdram reaches idle state to begin normal operation. if the system uses burst auto refresh during nor- mal operation, it is recommended to use burst 8192 auto refresh cycles for 256mb and burst 4096 auto refresh cycles for 128mb and 64mb immediately after exiting in self refresh mode. d. device operations (continued) the time required to complete the auto refresh operation is speci- fied by t rc (min). the minimum number of clock cycles required can be calculated by driving t rc with clock cycle time and them rounding up to the next higher integer. the auto refresh command must be followed by nop's until the auto refresh operation is com- pleted. all banks will be in the idle state at the end of auto refresh operation. the auto refresh is the preferred refresh mode when the sdram is being used for normal data transactions. the 64mb and 128mb sdram?s auto refresh cycle can be performed once in 15.6us or a burst of 4096 auto refresh cycles once in 64ms. the 256mb sdram?s auto refresh cycle can be performed once in 7.8us or a burst of 8192 auto refresh cycles once in 64ms.
cmos sdram device operations electronics mobile dram (v dd 2.5v, v ddq 1.8v & 2.5v) 1) clock suspended during write (bl=4) 1. clock suspend wr d 0 d 1 d 2 d 3 d 0 d 1 d 2 d 3 clk cmd cke internal clk dq(cl2) dq(cl3) masked by cke 2) clock suspended during read (bl=4) d 0 not written 1) write mask (bl=4) 2. dqm operation wr d 0 d 1 d 3 d 0 d 1 d 3 clk cmd dqm dq(cl2) dq(cl3) masked bydqm 2) read mask (bl=4) rd q 0 q 2 q 3 q 1 q 2 q 3 masked by dqm dqm to data-in mask = 0 dqm to data-out mask = 2 hi-z hi-z 3) dqm with clock suspended (full page read) *2 rd clk cmd cke dq(cl2) dq(cl3) q 0 q 4 q 7 q 8 q 2 q 3 q 6 q 7 q 1 hi-z hi-z hi-z hi-z hi-z hi-z dqm *note : 1. cke to clk disable/enable = 1clk. 2. dqm makes data out hi-z after 2clks which should masked by cke " l" 3. dqm masks both data-in and data-out. e. basic feature and function descriptions rd q 0 q 1 q 2 q 0 q 1 q 2 q 3 masked by cke q 3 suspended dout q 6 q 5 clk cmd cke internal clk dq(cl2) dq(cl3) clk cmd dqm dq(cl2) dq(cl3)
cmos sdram device operations electronics mobile dram (v dd 2.5v, v ddq 1.8v & 2.5v) 1) read interrupted by read (bl=4) *1 3. cas interrupt (i) clk cmd add rd rd a b qa 0 qb 1 qb 2 qb 3 qb 0 qa 0 qb 1 qb 2 qb 3 qb 0 tccd *2 2) write interrupted by write (bl=2) 3) write interrupted by read (bl=2) wr wr a b tccd *2 da 0 db 1 db 0 tcdl *3 clk cmd add dq wr rd a b tccd *2 tcdl *3 da 0 qb 1 qb 0 da 0 qb 1 qb 0 dq(cl2) dq(cl3) *note : 1. by " interrupt", it is meant to stop burst read/write by external command before the end of burst. by " cas interrupt", to stop burst read/write by cas access ; read and write. 2. t ccd : cas to cas delay. (=1clk) 3. t cdl : last data in to new column address delay. (=1clk) dq(cl2) dq(cl3) clk cmd add
cmos sdram device operations electronics mobile dram (v dd 2.5v, v ddq 1.8v & 2.5v) 4. cas interrupt (ii) : read interrupted by write & dqm *note : 1. to prevent bus contention, there should be at least one gap between data in and data out. d 1 d 2 rd d 3 wr d 0 d 1 d 2 d 3 d 0 d 1 d 2 d 3 d 0 rd wr rd wr hi-z hi-z rd wr q 0 d 1 d 2 d 3 d 0 *1 hi-z (a) cl=2, bl=4 clk i) cmd dqm dq ii) cmd dqm dq iii) cmd dqm dq iv) cmd dqm dq (b) cl=3, bl=4 clk i) cmd dqm dq d 1 d 2 rd d 3 wr d 0 d 1 d 2 d 3 d 0 d 1 d 2 d 3 d 0 rd wr rd wr d 1 d 2 d 3 d 0 rd wr rd wr d 1 d 2 d 3 d 0 hi-z ii) cmd dqm dq iii) cmd dqm dq iii) cmd dqm dq iv) cmd dqm dq q 0 *1 hi-z
cmos sdram device operations electronics mobile dram (v dd 2.5v, v ddq 1.8v & 2.5v) *note : 1. to prevent bus contention, dqm should be issued which makes at least one gap between data in and data out. 2. to inhibit invalid write, dqm should be issued. 3. this precharge command and burst write command should be of the same bank, otherwise it is not precharge interrupt but only another bank precharge of four banks operation. 5. write interrupted by precharge & dqm 6. precharge trdl *1 2) normal read (bl=4) clk cmd dq(cl2) dq(cl3) rd pre q 0 q 1 q 2 q 3 q 0 q 1 q 2 q 3 1 2 *note : 1 . samsung can support t rdl =1clk and trdl=2clk for all memory devices. samsung recommends trdl=2 clk. 2. number of valid output data after row precharge : 1, 2 for cas latency = 2, 3 respectively. 3. the row active command of the precharge bank can be issued after t rp from this point. the new read/write command of other activated bank can be issued from this point. at burst read/write with auto precharge, cas interrupt of the same bank is illegal 4. tdal defined last data in to active delay. samsung can support tdal=1clk+20ns and 2clk+20ns ,recommends tdal=2clk+20ns. 7. auto precharge d 0 d 1 d 2 clk cmd dq wr d 3 1) normal write (bl=4) 2) normal read (bl=4) clk cmd dq(cl2) dq(cl3) rd q 0 q 1 q 2 q 3 q 0 q 1 q 2 q 3 auto precharge starts *3 *2 d 0 d 1 d 2 clk cmd dqm dq masked by dqm wr pre *3 *2 1) trdl = 1 clk 2) trdl = 2clk auto precharge starts @trdl=1clk *3 auto precharge starts@trdl=2clk *3 d 0 d 1 d 2 clk cmd dq wr pre d 3 1) normal write bl=4 & trdl=2clk d 0 d 1 d 2 clk cmd dq wr pre d 3 bl=4 & trdl=1clk trdl *1 d 0 d 1 d 2 clk cmd dqm dq masked by dqm wr pre *3 *2 act d 0 d 1 d 2 cmd dq wr d 3 act trdl =1clk trdl =2clk tdal =1clk +20ns *4 tdal =2clk +20ns *4
cmos sdram device operations electronics mobile dram (v dd 2.5v, v ddq 1.8v & 2.5v) *note : 1 . samsung can support t rdl =1clk and trdl=2clk for all memory devices. samsung recommends trdl=2 clk. 2. t bdl : 1 clk ; last data in to burst stop delay. read or write burst stop command is valid at every burst length. 3. number of valid output data after row precharge or burst stop : 1, 2 for cas latency= 2, 3 respectively. 4. pre : all banks precharge is necessary. mrs can be issued only at all banks precharge state. 8. burst stop & interrupted by precharge 3) read interrupted by precharge (bl=4) clk cmd dq(cl2) dq(cl3) rd pre q 0 q 1 q 0 q 1 1 2 9. mrs clk pre 1) mode register set 4) read burst stop (bl=4) clk cmd dq(cl2) dq(cl3) rd stop q 0 q 1 q 0 q 1 1 2 mrs act *4 trp 2clk cmd d 0 d 1 d 2 clk cmd dq wr pre 1) normal write trdl *1 d 0 d 1 d 2 clk cmd dq wr stop d 3 2) write burst stop (bl=8) dqm dqm tbdl *2 d 0 d 1 d 2 clk cmd dq wr pre trdl *1 dqm bl=4 & trdl=1clk bl=4 & trdl=2clk
cmos sdram device operations electronics mobile dram (v dd 2.5v, v ddq 1.8v & 2.5v) *note : 1. active power down : one or more banks active state. 2. precharge power down : all banks precharge state. 3. the auto refresh is the same as cbr refresh of conventional dram. no precharge commands are required after auto refresh command. during t rc from auto refresh command, any other command can not be accepted. 4. before executing auto/self refresh command, all banks must be idle state. 5. mrs, bank active, auto/self refresh, power down mode entry. 6. during self refresh mode, refresh interval and refresh operation are performed internally. after self refresh entry, self refresh mode is kept while cke is low. during self refresh mode, all inputs except cke will be don't cared, and outputs will be in hi-z state. for the time interval of t rc from self refresh exit command, any other command can not be accepted. before/after self refresh mode, burst auto refresh cycle (4096 cycles for 64mb & 128mb, 8192 cycles for 256mb) is recommended. 10. clock suspend exit & power down exit clk cke cmd rd 1) clock suspend (=active power down) exit tss clk cke cmd 2) power down (=precharge power down) exit *1 *5 internal clk nop tss *2 internal clk 11. auto refresh & self refresh clk cmd 1) auto refresh cke pre ar cmd *4 trp trc clk cmd 2) self refresh cke pre sr cmd *4 trp trc note 6 act ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~
cmos sdram device operations electronics mobile dram (v dd 2.5v, v ddq 1.8v & 2.5v) 12. about burst type control at mrs a 3 = "0". see the burst sequence table. (bl=4, 8) bl=1, 2, 4, 8 and full page. at mrs a 3 = "1". see the burst sequence table. (bl=4, 8) bl=4, 8. at bl=1, 2 interleave counting = sequential counting every cycle read/write command with random column address can realize random column access. that is similar to extended data out (edo) operation of conventional dram. basic mode random mode sequential counting interleave counting random column access t ccd = 1 clk 13. about burst length control at mrs a 2,1,0 = "000". at auto precharge, t ras should not be violated. at mrs a 2,1,0 = "001". at auto precharge, t ras should not be violated. before the end of burst, row precharge command of the same bank stops read/write burst with row precharge. t rdl = 2 with dqm, valid dq after burst stop is 1, 2 for cas latency 2, 3 respectively. during read/write burst with auto precharge, ras interrupt can not be issued. basic mode interrupt mode 1 2 ras interrupt (interrupted by precharge) at mrs a 2,1,0 = "010". at mrs a 2,1,0 = "011". at mrs a 2,1,0 = "111". wrap around mode(infinite burst length) should be stopped by burst stop. ras interrupt or cas interrupt 4 8 full page at mrs a 9 = "1". read burst =1, 2, 4, 8, full page write burst =1 at auto precharge of write, t ras should not be violated. t bdl = 1, valid dq after burst stop is 1, 2 for cas latency 2, 3 respectively using burst stop command, any burst length control is possible. before the end of burst, new read/write stops read/write burst and starts new read/write burst. during read/write burst with auto precharge, cas interrupt can not be issued. brsw burst stop cas interrupt random mode special mode
cmos sdram device operations electronics mobile dram (v dd 2.5v, v ddq 1.8v & 2.5v) x x x ca, a 10 /ap ra a 10 /ap x op code x x x ca, a 10 /ap ca, a 10 /ap ra a 10 /ap x x x x ca, a 10 /ap ca, a 10 /ap ra a 10 /ap x x x x ca, a 10 /ap ca, a 10 /ap ra a 10 /ap x x x x ca, a 10 /ap ra, ra 10 x x x x ca, a 10 /ap ra, ra 10 x x x x ca ra a 10 /ap function truth table (table 1) current state cs ras cas we ba addr action note h l l l l l l l h l l l l l l l h l l l l l l l h l l l l l l l h l l l l l h l l l l l h l l l l l idle row active read write read with auto precharge write with auto precharge pre- charging nop nop illegal illegal row (& bank) active ; latch ra nop auto refresh or self refresh mode register access nop nop illegal begin read ; latch ca ; determine ap begin write ; latch ca ; determine ap illegal precharge illegal nop (continue burst to end --> row active) nop (continue burst to end --> row active) term burst --> row active term burst, new read, determine ap term burst, new write, determine ap illegal term burst, precharge timing for reads illegal nop (continue burst to end --> row active) nop (continue burst to end --> row active) term burst --> row active term burst, new read, determine ap term burst, new write, determine ap illegal term burst, precharge timing for writes illegal nop (continue burst to end --> precharge) nop (continue burst to end --> precharge) illegal illegal illegal illegal nop (continue burst to end --> precharge) nop (continue burst to end --> precharge) illegal illegal illegal illegal nop --> idle after t rp nop --> idle after t rp illegal illegal illegal nop --> idle after t rp x x x ba ba ba x op code x x x ba ba ba ba x x x x ba ba ba ba x x x x ba ba ba ba x x x x ba ba x x x x ba ba x x x x ba ba ba x h h h l l l l x h h h h l l l x h h h h l l l x h h h h l l l x h h h l l x h h h l l x h h h l l x h h l h h l l x h h l l h h l x h h l l h h l x h h l l h h l x h h l h l x h h l h l x h h l h h x h l x h l h l x h l h l h l x x h l h l h l x x h l h l h l x x h l x x x x h l x x x x h l x h l 2 2 4 5 5 2 2 3 2 3 3 2 3 2 2 2 2 2 4
cmos sdram device operations electronics mobile dram (v dd 2.5v, v ddq 1.8v & 2.5v) function truth table (table 1) current state cs ras cas we ba addr action note l h l l l l l l h l l l l h l l l l x x x x ca ra a 10 /ap x x x x x x x x x x x row activating refreshing illegal nop --> row active after t rcd nop --> row active after t rcd illegal illegal illegal illegal illegal nop --> idle after t rc nop --> idle after t rc illegal illegal illegal nop --> idle after 2 clocks nop --> idle after 2 clocks illegal illegal illegal x x x x ba ba ba x x x x x x x x x x x l x h h h l l l x h h l l x h h h l l x h h l h h l x h l h l x h h l x x x h l x h l x x x x x x x h l x x 2 2 2 2 mode register accessing *note : 1. all entries assume the cke was active (high) during the precharge clock and the current clock cycle. 2. illegal to bank in specified state ; function may be iegal in the bank indicated by ba, depending on the state of that bank. 3. must satisfy bus contention, bus turn around, and/or write recovery requirements. 4. nop to bank precharging or in idle state. may precharge bank indicated by ba (and a 10 /ap). 5. illegal if any bank is not idle. abbreviations : ra = row address ba = bank address nop = no operation command ca = column address ap = auto precharge
cmos sdram device operations electronics mobile dram (v dd 2.5v, v ddq 1.8v & 2.5v) function truth table (table 2) current state cs ras cas we addr action note x h l l l l x x h l l l l x x h l l l l l l x x x x x x x x x x x x x x x x x x x x x x x x ra x op code x x x x x self refresh invalid exit self refresh --> idle after t rfc (abi) exit self refresh --> idle after t rfc (abi) illegal illegal illegal nop (maintain self refresh) invalid exit power down --> abi exit power down --> abi illegal illegal illegal nop (maintain low power mode) refer to table 1 enter power down enter power down illegal illegal row (& bank) active enter self refresh mode register access nop refer to operations in table 1 begin clock suspend next cycle exit clock suspend next cycle maintain clock suspend x x h h h l x x x h h h l x x x h h h l l l x x x x x x x h h l x x x x h h l x x x x h h l h l l x x x x x x x h l x x x x x h l x x x x x h l x h h l x x x x x 6 6 7 7 8 8 8 9 9 all banks idle *note : 6. cke low to high transition is asynchronous. 7. cke low to high transition is asynchronous if restarts internal clock. a minimum setup time 1clk + t ss must be satisfied before any command other than exit. 8. power down and self refresh can be entered only from the both banks idle state. 9. must be a legal command. abbreviations : abi = all banks idle, ra = row address cke (n-1) h l l l l l l h l l l l l l h h h h h h h h l h h l l x h h h h h l x h h h h h l h l l l l l l l l h l h l cke n all banks precharge power down any state other than listed above
mobile dram (v dd 2.5v, v ddq 1.8v & 2.5v) timing diagram cmos sdram electronics single bit read - write - read cycle(same page) @cas latency=3, burst length=1 power up sequence read & write cycle at same bank @burst length=4, trdl=1clk read & write cycle at same bank @burst length=4, trdl=2clk page read & write cycle at same bank @burst length=4 , trdl=1clk page read & write cycle at same bank @burst length=4 , trdl=2clk page read cycle at different bank @burst length=4 page write cycle at different bank @burst length=4, trdl=1clk page write cycle at different bank @burst length=4, trdl=2clk read & write cycle at different bank @burst length=4 read & write cycle with auto precharge l @burst length=4 read & write cycle with auto precharge ll @burst length=4 clock suspension & dqm operation cycle @cas letency=2, burst length=4 read interrupted by precharge command & read burst stop cycle @ full page burst write interrupted by precharge command & write burst stop cycle @ full page burst, trdl=1clk write interrupted by precharge command & write burst stop cycle @ full page burst, trdl=2clk active/precharge power dower down mode @cas latency=2 burst length=4 self refresh entry & exit cycle & exit cycle mode register set cycle auto refresh cycle
mobile dram (v dd 2.5v, v ddq 1.8v & 2.5v) timing diagram cmos sdram electronics 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 single bit read-write-read cycle(same page) @cas latency=3, burst length=1 : don't care trcd *note 1 tss tsh trp tccd tss tsh trac tsac tslz toh tsh tss tss tsh tss tsh clock cke cs ras cas addr ba 0 ~ ba 1 a 10 /ap dq we dqm row active read write read row active precharge tch tcc tcl tras trc high tsh tsh tss tss *note 2,3 *note 2,3 *note 4 *note 4 *note 3 *note 3 *note 3 rb cc cb ca ra bs bs bs bs bs bs ra rb qc db qa *note 2,3 *note 2 *note 2
mobile dram (v dd 2.5v, v ddq 1.8v & 2.5v) timing diagram cmos sdram electronics *note : 1. all input except cke & dqm can be don't care when cs is high at the clk high going edge. 2. bank active & read/write are controlled by ba0~ba1. 3. enable and disable auto precharge function are controlled by a10/ap in read/write command 4. a10/ap and ba0~ba1 control bank precharge when precharge command is asserted. 64mb/128mb 256mb active & read/write ba0 ba1 ba0 ba1 0 0 0 0 bank a 0 1 1 0 bank b 1 0 0 1 bank c 1 1 1 1 bank d a10/ap 64mb/128mb 256mb operation ba0 ba1 ba0 ba1 0 0 0 0 0 disable auto precharge, leave bank a active at end of burst. 0 1 1 0 disable auto precharge, leave bank b active at end of burst. 1 0 0 1 disable auto precharge, leave bank c active at end of burst. 1 1 1 1 disable auto precharge, leave bank d active at end of burst. 1 0 0 0 0 enable auto precharge, precharge bank a at end of burst. 0 1 1 0 enable auto precharge, precharge bank b at end of burst. 1 0 0 1 enable auto precharge, precharge bank c at end of burst. 1 1 1 1 enable auto precharge, precharge bank d at end of burst. a10/ap 64mb/128mb 256mb precharge ba0 ba1 ba0 ba1 0 0 0 0 0 bank a 0 0 1 1 0 bank b 0 1 0 0 1 bank c 0 1 1 1 1 bank d 1 x x x x all banks
mobile dram (v dd 2.5v, v ddq 1.8v & 2.5v) timing diagram cmos sdram electronics 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 power up sequence : don't care clock cke cs ras cas addr ba 0 a 10 /ap dq we dqm precharge auto refresh auto refresh mode register set row active ba 1 raa raa (all banks) (a-bank) trp trc high level is necessary high-z high level is necessary trc key ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ 1. apply power and start clock, attempt to maintain cke= "h", dqm= "h" and the other pins are nop condition at the inputs. 2. power is applied to vdd and vddq (simultaneously). 3. maintain stable power, stable clock and nop input condition for a minimum of 200us. 4. issue precharge commands for all banks of the devices. 5. issue 2 or more auto-refresh commands. 6. issue a mode register set command to initialize the mode register. note : 1. in order to assert normal mrs, ba0 and ba1 should set "0" absolutely. power up sequence
mobile dram (v dd 2.5v, v ddq 1.8v & 2.5v) timing diagram cmos sdram electronics 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 read & write cycle at same bank @burst length=4, trdl=1clk high : don't care *note : 1. minimum row cycle times is required to complete internal dram operation. 2. row precharge can interrupt burst on any cycle. [cas latency - 1] number of valid output data is available after row precharge. last valid output will be hi-z(t shz ) after the clcok. 3. access time from row active command. t cc *(t rcd + cas latency - 1) + t sac 4. ouput will be hi-z after the end of burst. (1, 2, 4, 8 & full page bit burst) *note 1 trc trcd *note 2 trdl trdl tshz *note 4 tshz *note 4 toh trac *note 3 tsac tsac trac *note 3 toh ba 0 ba 1 a 10 /ap cl=2 cl=3 dq addr cas ras cs cke clock ra rb qa0 qa1 qa2 qa3 qa0 qa1 qa2 qa3 db0 db1 db2 db3 db0 db1 db2 db3 ra ca rb cb we dqm row active (a-bank) precharge (a-bank) row active (a-bank) write (a-bank) precharge (a-bank) read (a-bank)
mobile dram (v dd 2.5v, v ddq 1.8v & 2.5v) timing diagram cmos sdram electronics 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 read & write cycle at same bank @burst length=4, trdl=2clk high : don't care *note : 1. minimum row cycle times is required to complete internal dram operation. 2. row precharge can interrupt burst on any cycle. [cas latency - 1] number of valid output data is available after row precharge. last valid output will be hi-z(t shz ) after the clcok. 3. access time from row active command. t cc *(t rcd + cas latency - 1) + t sac 4. ouput will be hi-z after the end of burst. (1, 2, 4, 8 & full page bit burst) *note 1 trc trcd *note 2 trdl trdl tshz *note 4 tshz *note 4 toh trac *note 3 tsac tsac trac *note 3 toh ba 0 ba 1 a 10 /ap cl=2 cl=3 dq addr cas ras cs cke clock ra rb qa0 qa1 qa2 qa3 qa0 qa1 qa2 qa3 db0 db1 db2 db3 db0 db1 db2 db3 ra ca rb cb we dqm row active (a-bank) precharge (a-bank) row active (a-bank) write (a-bank) precharge (a-bank) read (a-bank)
mobile dram (v dd 2.5v, v ddq 1.8v & 2.5v) timing diagram cmos sdram electronics 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 page read & write cycle at same bank @burst length=4, trdl=1clk high row active (a-bank) read (a-bank) write (a-bank) precharge (a-bank) : don't care *note : 1. to write data before burst read ends, dqm should be asserted three cycle prior to write command to avoid bus contention. 2. row precharge will interrupt writing. last data input, t rdl before row precharge, will be written. 3. dqm should mask invalid input data on precharge command cycle when asserting precharge before end of burst. input data after row precharge cycle will be masked internally. 4. tdal, last data in to active delay, is 1clk + 20ns read (a-bank) trcd *note 2 trdl *note 1 *note 3 tcdl qa0 qa1 qb0 qb1 qb2 qa0 qa1 qb0 qb1 dc0 dc1 dd0 dd1 dc0 dc1 dd0 dd1 write (a-bank) ba 0 ba 1 a 10 /ap cl=2 cl=3 dq addr cas ras cs cke clock we dqm ra ca cb cc cd ra tdal *note 4 rb rb row adiwe (a-bank)
mobile dram (v dd 2.5v, v ddq 1.8v & 2.5v) timing diagram cmos sdram electronics 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 page read & write cycle at same bank @burst length=4, trdl=2clk high row active (a-bank) read (a-bank) write (a-bank) precharge (a-bank) : don't care *note : 1. to write data before burst read ends, dqm should be asserted three cycle prior to write command to avoid bus contention. 2. row precharge will interrupt writing. last data input, t rdl before row precharge, will be written. 3. dqm should mask invalid input data on precharge command cycle when asserting precharge before end of burst. input data after row precharge cycle will be masked internally. 4. tdal ,last data in to active delay, is 2clk + 20ns. read (a-bank) trcd *note 2 trdl *note 1 *note 3 tcdl qa0 qa1 qb0 qb1 qb2 qa0 qa1 qb0 qb1 dc0 dc1 dd0 dd1 dc0 dc1 dd0 dd1 write (a-bank) ba 0 ba 1 a 10 /ap cl=2 cl=3 dq addr cas ras cs cke clock we dqm ra ca cb cc cd ra tdal *note 4 row active (a-bank) rb rb
mobile dram (v dd 2.5v, v ddq 1.8v & 2.5v) timing diagram cmos sdram electronics 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 page read cycle at different bank @burst length=4 high row active (a-bank) read (a-bank) read (c-bank) precharge (b-bank) read (d-bank) : don't care *note : 1. cs can be don't cared when ras , cas and we are high at the clock high going dege. 2. to interrupt a burst read by row precharge, both the read and the precharge banks must be the same. row active (b-bank) *note 2 *note 1 row acive (c-bank) read (b-bank) precharge (a-bank) row active (d-bank) precharge (c-bank) precharge (d-bank) ba 0 ba 1 a 10 /ap cl=2 cl=3 dq addr cas ras cs cke clock we dqm qaa0 qaa1 qaa2 qbb0 qbb1 qbb2 qcc0 qcc1 qcc2 qdd0 qdd1 qdd2 qaa0 qaa1 qaa2 qbb0 qbb1 qbb2 qcc0 qcc1 qcc2 qdd0 qdd1 qdd2 raa rbb rcc rdd raa rbb caa rcc cbb rdd ccc cdd
mobile dram (v dd 2.5v, v ddq 1.8v & 2.5v) timing diagram cmos sdram electronics 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 page write cycle at different bank @burst length=4, trdl=1clk high row active (a-bank) write (a-bank) row active (d-bank) write (d-bank) : don't care *note : 1. to interrupt burst write by row precharge, dqm should be asserted to mask invalid input data. 2. to interrupt burst write by row precharge, both the write and the precharge banks must be the same. row active (b-bank) trdl row active (c-bank) precharge (all banks) tcdl write (b-bank) write (c-bank) *note 1 ba 0 ba 1 dq addr cas ras cs cke clock we dqm a 10 /ap raa rbb caa cbb rcc rdd ccc cdd rcc rdd raa rbb *note 2 daa0 daa1 daa2 daa3 dbb0 dbb1 dbb2 dbb3 dcc0 dcc1 ddd0 ddd1 ddd2
mobile dram (v dd 2.5v, v ddq 1.8v & 2.5v) timing diagram cmos sdram electronics 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 page write cycle at different bank @burst length=4, trdl=2clk high row active (a-bank) write (a-bank) row active (d-bank) write (d-bank) : don't care *note : 1. to interrupt burst write by row precharge, dqm should be asserted to mask invalid input data. 2. to interrupt burst write by row precharge, both the write and the precharge banks must be the same. row active (b-bank) trdl row active (c-bank) precharge (all banks) tcdl write (b-bank) write (c-bank) *note 1 ba 0 ba 1 dq addr cas ras cs cke clock we dqm a 10 /ap raa rbb caa cbb rcc rdd ccc cdd rcc rdd raa rbb daa0 daa1 daa2 daa3 dbb0 dbb1 dbb2 dbb3 dcc0 dcc1 ddd0 ddd1 ddd2 *note 2
mobile dram (v dd 2.5v, v ddq 1.8v & 2.5v) timing diagram cmos sdram electronics 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 read & write cycle at different bank @burst length=4 high raa row active (a-bank) write (d-bank) row active (b-bank) : don't care *note : 1. t cdl should be met to complete write. read (a-bank) raa cdb rbc *note 1 tcdl rdb caa rbc row active (d-bank) precharge (a-bank) read (b-bank) cbc rdb ba 0 ba 1 a 10 /ap cl=2 cl=3 dq addr cas ras cs cke clock we dqm qaa0 qaa1 qaa2 qaa3 qaa0 qaa1 qaa2 qaa3 ddb0 ddb1 ddb2 ddb3 ddb0 ddb1 ddb2 ddb3 qbc0 qbc1 qbc2 qbc0 qbc1
mobile dram (v dd 2.5v, v ddq 1.8v & 2.5v) timing diagram cmos sdram electronics 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 read & write cycle with auto precharge i @burst length=4 high row active (a-bank) : don't care *note1: when read(write) command with auto precharge is issued at a-bank after a and b bank activation. - if read(write) command without auto precharge is issued at b-bank before a-bank auto precharge starts, a-bank auto precharge will start at b-bank read command input point . - any command can not be issued at a-bank during trp after a-bank auto precharge starts. row active (b-bank) read with auto pre charge (a-bank) write with auto precharge (a-bank) row active (a-bank) ba 0 a 10 /ap cl=2 cl=3 dq addr cas ras cs cke clock we dqm qaa0 qaa1 qbb0 qbb1 qaa0 qaa1 qbb0 qbb1 raa rbb caa raa rbb rac cbb qbb2 qbb3 read without auto precharge(b-bank) auto precharge start point (a-bank)* note1 precharge (b-bank) dac0 dac1 dac0 dac1 qbb2 qbb3 cac rac ba 1
mobile dram (v dd 2.5v, v ddq 1.8v & 2.5v) timing diagram cmos sdram electronics 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 read & write cycle with auto precharge ii @burst length=4 high row active (a-bank) : don't care *note 1: any command to a-bank is not allowed in this period. trp is determined from at auto precharge start point read with auto precharge (a-bank) auto precharge start point (a-bank) row active (b-bank) read with auto precharge (b-bank) ba 0 a 10 /ap cl=2 cl=3 dq addr cas ras cs cke clock we dqm qa0 qa1 qa2 qa3 qa0 qa1 qa2 qa3 qb0 qb1 qb2 qb3 qb0 qb1 qb2 qb3 ra ca ra cb rb rb *note1 auto precharge start point (b-bank) ba 1
mobile dram (v dd 2.5v, v ddq 1.8v & 2.5v) timing diagram cmos sdram electronics 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 clock suspension & dqm operation cycle @cas latency=2, burst length=4 ra row active clock suspension read write dqm : don't care clock suspension read *note 1 tshz tshz write dqm write read dqm *note1 : dqm is needed to prevent bus contention. ba 0 ba 1 dq addr cas ras cs cke clock we dqm a 10 /ap ra ca cb cc dc2 dc0 qb1 qb0 qa3 qa2 qa1 qa0
mobile dram (v dd 2.5v, v ddq 1.8v & 2.5v) timing diagram cmos sdram electronics 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 read interrupted by precharge command & read burst stop cycle @ full page burst high row active (a-bank) : don't care *note : 1. at full page mode, burst is finished by burst stop or precharge. 2. about the valid dqs after burst stop, it is same as the case of ras interrupt. both cases are illustrated above timing diagram. see the label 1, 2 on them. but at burst write, burst stop and ras interrupt should be compared carefully. refer the timing diagram of "full page write burst stop cycle". 3. burst stop is valid at every burst length. precharge (a-bank) burst stop read (a-bank) read (a-bank) 1 2 1 2 ba 0 ba 1 a 10 /ap cl=2 cl=3 dq addr cas ras cs cke clock we dqm qaa0 qaa1 qaa2 qaa3 qaa4 qaa0 qaa1 qaa2 qaa3 qaa4 qab0 qab1 qab2 qab3 qab4 qab5 qab0 qab1 qab2 qab3 qab4 qab5 raa caa cab raa
mobile dram (v dd 2.5v, v ddq 1.8v & 2.5v) timing diagram cmos sdram electronics 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 write interrupted by precharge command & write burst stop cycle @ full page burst, trdl=1clk row active (a-bank) burst stop write (a-bank) precharge (a-bank) : don't care write (a-bank) *note 1,2 tbdl *note : 1. at full page mode, burst is finished by burst stop or precharge. 2. data-in at the cycle of interrupted by precharge can not be written into the corresponding memory cell. it is defined by ac parameter of t rdl. dqm at write interrupted by precharge command is needed to prevent invalid write. dqm should mask invalid input data on precharge command cycle when asserting precharge before end of burst. input data after row precharge cycle will be masked internally. 3. burst stop is valid at every burst length. high trdl ba 0 ba 1 dq addr cas ras cs cke clock we dqm a 10 /ap daa0 daa1 daa2 daa3 daa4 dab0 dab1 dab2 dab3 dab4 dab5 raa caa cab raa *note 1
mobile dram (v dd 2.5v, v ddq 1.8v & 2.5v) timing diagram cmos sdram electronics 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 write interrupted by precharge command & write burst stop cycle @ full page burst, trdl=2clk row active (a-bank) burst stop write (a-bank) precharge (a-bank) : don't care write (a-bank) tbdl *note : 1. at full page mode, burst is finished by burst stop or precharge. 2. data-in at the cycle of interrupted by precharge can not be written into the corresponding memory cell. it is defined by ac parameter of t rdl. dqm at write interrupted by precharge command is needed to prevent invalid write. dqm should mask invalid input data on precharge command cycle when asserting precharge before end of burst. input data after row precharge cycle will be masked internally. 3. burst stop is valid at every burst length. high trdl ba 0 ba 1 dq addr cas ras cs cke clock we dqm a 10 /ap daa0 daa1 daa2 daa3 daa4 dab0 dab1 dab2 dab3 dab4 dab5 raa caa cab raa *note 1,2 *note 1
mobile dram (v dd 2.5v, v ddq 1.8v & 2.5v) timing diagram cmos sdram electronics 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 active/precharge power down mode @cas latency=2, burst length=4 precharge power-down entry : don ? t care *note : 1. both banks should be in idle state prior to entering precharge power down mode. 2. cke should be set high at least 1clk + tss prior to row active command. 3. can not violate minimum refresh specification. (64ms) *note 1 precharge tss *note 2 ba dq addr cas ras cs cke clock we dqm a 10 /ap tss tss ra ca ra qa0 qa1 qa2 row active precharge power-down exit active power-down entry active power-down exit read tshz *note 3 *note 2 ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~
mobile dram (v dd 2.5v, v ddq 1.8v & 2.5v) timing diagram cmos sdram electronics 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 self refresh entry & exit cycle self refresh entry : don't care *note : to enter self refresh mode 1. cs , ras & cas with cke should be low at the same clcok cycle. 2. after 1 clock cycle, all the inputs including the system clock can be don't care except for cke. 3. the device remains in self refresh mode as long as cke stays "low". cf.) once the device enters self refresh mode, minimum t ras is required before exit from self refresh. to exit self refresh mode 4. system clock restart and be stable before returning cke high. 5. cs starts from high. 6. minimum t rc is required after cke going high to complete self refresh exit. 7. 4k cycle(64mb ,128mb) or 8k cycle(256mb) of burst auto refresh is required before self refresh entry and after self refresh exit if the system uses burst refresh. *note 1 *note 7 hi-z hi-z self refresh exit auto refresh tss *note 2 *note 3 *note 4 trcmin *note 6 *note 5 ba 0 ~ba 1 dq addr cas ras cs cke clock we dqm a 10 /ap ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~
mobile dram (v dd 2.5v, v ddq 1.8v & 2.5v) timing diagram cmos sdram electronics 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 mode register set cycle high mrs auto refresh : don't care *note : 1. cs , ras , cas , ba0 , ba1 & we activation at the same clock cycle with address key will set internal mode register. 2. minimum 2 clock cycles should be met before new ras activation. 3. please refer to mode register set table. new command new command hi-z hi-z trc high mode register set cycle * all banks precharge should be completed before mode register set cycle and auto refresh cycle. auto refresh cycle dq addr cas ras cs cke clock we dqm key ra *note 3 *note 1 *note 2 ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ 0 1 2 3 4 5 6 7 8 9 10 ba1 ba0

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